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FEATURES 16-Bit Sigma-Delta ADC 1.2 MSPS Output Word Rate 32/16 Oversampling Ratio Low-Pass and Band-Pass Digital Filter Linear Phase On-Chip 2.5 V Voltage Reference Standby Mode Flexible Parallel or Serial Interface Crystal Oscillator Single +5 V Supply
AVDD AGND VIN(+) VIN(-)
16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC AD7723
FUNCTIONAL BLOCK DIAGRAM
AD7723
2.5V REFERENCE REF2 REF1 DVDD DGND
MODULATOR
FIR FILTER
UNI HALF_PWR STBY MODE 1 MODE 2 SYNC DVDD /CS CFMT/RD DGND/DRDY DGND/DB0
XTAL CLOCK
XTAL_OFF XTAL CLKIN DGND/DB15 DGND/DB14 SCR/DB13 SLDR/DB12 SLP/DB11 TSI/DB10 FSO/DB9
CONTROL LOGIC
DGND/ DGND/ DGND/ DOE/ SFMT/ FSI/ SCO/ SDO/ DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8
GENERAL DESCRIPTION
The AD7723 is a complete 16-bit, sigma-delta ADC. The part operates from a +5 V supply. The analog input is continuously sampled, eliminating the need for an external sample-and-hold. The modulator output is processed by a finite impulse response (FIR) digital filter. The on-chip filtering combined with a high oversampling ratio reduces the external antialias requirements to first order in most cases. The digital filter frequency response can be programmed to be either low pass or band pass. The AD7723 provides 16-bit performance for input bandwidths up to 460 kHz at an output word rate up to 1.2 MHz. The sample rate, filter corner frequencies and output word rate are set by the crystal oscillator or external clock frequency. Data can be read from the device in either serial or parallel format. A stereo mode allows data from two devices to share a single serial data line. All interface modes offer easy, high speed connections to modern digital signal processors.
The part provides an on-chip 2.5 V reference. Alternatively, an external reference can be used. A power-down mode reduces the idle power consumption to 200 W. The AD7723 is available in a 44-lead PQFP package and is specified over the industrial temperature range from -40C to +85C. Two input modes are provided, allowing both unipolar and bipolar input ranges.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
AD7723-SPECIFICATIONS1 f
Parameter
DYNAMIC SPECIFICATIONS2, 3 Decimate by 32 Bipolar Mode Signal to Noise Full Power Half Power Total Harmonic Distortion4 Spurious Free Dynamic Range4 Unipolar Mode Signal to Noise Total Harmonic Distortion4 Spurious Free Dynamic Range4 Bandpass Filter Mode Bipolar Mode Signal to Noise Decimate by 16 Bipolar Mode Signal to Noise
(AVDD = DVDD = +5 V 5%; AGND = AGND1 = AGND2 = DGND = 0 V; CLKIN = 19.2 MHz; REF2 = 2.5 V; TA = TMIN to TMAX ; unless otherwise noted)
Min B Version Typ Max Units
Test Conditions/Comments
HALF_PWR = 0 or 1 fCLKIN = 10 MHz When HALF-PWR = 1
2.5 V Reference 3 V Reference
87 88.5 86.5
90 91 89 -96
2.5 V Reference 3 V Reference 87 -89 -90
-90 -92 -90
dB dB dB dB dB dB dB dB dB
76
79
dB
Signal to Noise Total Harmonic Distortion4 Spurious Free Dynamic Range4 Unipolar Mode Signal to Noise Signal to Noise Total Harmonic Distortion4
Measurement Bandwidth = 0.383 x FO 2.5 V Reference 3 V Reference Measurement Bandwidth = 0.5 x FO 2.5 V Reference 3 V Reference 2.5 V Reference 3 V Reference Measurement Bandwidth = 0.383 x FO Measurement Bandwidth = 0.5 x FO
82 83 78
86 87 81.5 -88 -86 -90 -88 84 81 -89
dB dB dB dB dB dB dB dB dB dB
DIGITAL FILTER RESPONSE Low Pass Decimate by 32 0 kHz to fCLKIN /83.5 fCLKIN /66.9 fCLKIN /64 fCLKIN /51.9 to fCLKIN/2 Group Delay Settling Time Low Pass Decimate by 16 0 kHz to fCLKIN/41.75 fCLKIN /33.45 fCLKIN /32 fCLKIN /25.95 to fCLKIN /2 Group Delay Settling Time Band Pass Decimate by 32 fCLKIN /51.90 to fCLKIN /41.75 fCLKIN /62.95, fCLKIN/33.34 fCLKIN /64, fCLKIN /32 0 kHz to fCLKIN /83.5, fCLKIN /25.95 to fCLKIN /2 Group Delay Settling Time Output Data Rate, FO Decimate by 32 Decimate by 16 ANALOG INPUTS Full-Scale Input Span Bipolar Mode Unipolar Mode VIN(+) - VIN(-)
0.001 -3 -6 -90 1293/2fCLKIN 1293/fCLKIN 0.001 -3 -6 -90 541/2fCLKIN 541/fCLKIN 0.001 -3 -6 -90 1293/2fCLKIN 1293/fCLKIN fCLKIN /32 fCLKIN /16
dB dB dB dB
dB dB dB dB
dB dB dB dB
0
4/5 x VREF2 8/5 x VREF2
V V
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AD7723
Parameter
ANALOG INPUTS (Continued) Absolute Input Voltage Input Sampling Capacitance Input Sampling Rate, fCLKIN CLOCK CLKIN Duty Ratio REFERENCE REF1 Output Resistance Using Internal Reference REF2 Output Voltage REF2 Output Voltage Drift Using External Reference REF2 Input Impedance REF2 External Voltage Range STATIC PERFORMANCE Resolution Differential Nonlinearity Integral Nonlinearity DC CMRR Offset Error Gain Error 5 LOGIC INPUTS (Excluding CLKIN) VINH, Input High Voltage VINL, Input Low Voltage CLOCK INPUT (CLKIN) VINH, Input High Voltage VINL, Input Low Voltage ALL LOGIC INPUTS IIN, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD IAVDD DVDD IDVDD Power Consumption6 VIN = 0 V to DVDD
Test Conditions/Comments
VIN(+) and/or VIN(-)
Min
AGND
B Version Typ
Max
AVDD
Units
V pF MHz % k
2 19.2 45 3 2.39 2.54 60 4 2.5 2.69 55
V ppm/C k V Bits LSB LSB dB mV % FSR V V V V A pF V V V mA mA V mA mA W
REF1 = AGND 1.2 16 Guaranteed Monotonic
3.15
0.5 2 80 20 0.5 2.0
1
0.8 3.8 0.4 10 10 4.0 0.4 4.75 HALF_PWR = Logic Low HALF_PWR = Logic High 4.75 HALF_PWR = Logic Low HALF_PWR = Logic High Standby Mode 25 15 50 25 5.25 60 33 5.25 35 20 200
|IOUT| = 200 A |IOUT| = 1.6 mA
NOTES 1Operating temperature range is as follows: B Version: -40C to +85C. 2Typical values for SNR apply for parts soldered directly to a printed circuit board ground plane. 3Dynamic specifications apply for input signal frequencies from dc to 0.0240 x f CLKIN in decimate by 16 mode and from dc to 0.0120 x f CLKIN in decimate by 32 mode. 4When using the internal reference, THD and SFDR specifications apply only to input signals above 10 kHz with a 10 F decoupling capacitor between REF2 and AGND2. At frequencies below 10 kHz, THD degrades to 84 dB and SFDR degrades to 86 dB. 5Gain Error excludes Reference Error. 6CLKIN and digital inputs static and equal to 0 or DV DD. Specifications subject to change without notice.
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AD7723 TIMING SPECIFICATIONS
Parameter CLKIN Frequency CLKIN Period (tCLK = 1/fCLK) CLKIN Low Pulsewidth CLKIN High Pulsewidth CLKIN Rise Time CLKIN Fall Time FSI Setup Time FSI Hold Time FSI High Time1 CLKIN to SCO Delay SCO Period2, SCR = 1 SCO Period2, SCR = 0 SCO Transition to FSO High Delay SCO Transition to FSO Low Delay SCO Transition to SDO Valid Delay SCO Transition from FSI3 SDO Enable Delay Time SDO Disable Delay Time DRDY High Time2 Conversion Time2 (Refer to Tables I and II) CLKIN to DRDY Transition CLKIN to DATA Valid CS/RD Setup Time to CLKIN CS/RD Hold Time to CLKIN Data Access Time Bus Relinquish Time SYNC Input Pulsewidth SYNC Low Time before CLKIN Rising DRDY High Delay after Rising SYNC DRDY Low Delay after SYNC Low
NOTES 1FSO pulses are gated by the release of FSI (going low). 2Guaranteed by design. 3Frame Sync is initiated on the falling edge of CLKIN. Specifications subject to change without notice.
(AVDD = DVDD = +5 V 5%; AGND = AGND1 = DGND = 0 V; fCLKIN = 19.2 MHz; CL = 50 pF; SFMT = Logic Low or High, CFMT = Logic Low or High; TA = TMIN to TMAX unless otherwise noted)
Symbol FCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 Min 1 0.052 0.45 x t1 0.45 x t1 5 5 0 0 25 2 1 0 0 5 60 5 5 2 16/32 35 20 0 20 20 20 1 0 25 35 2049 35 35 50 35 Typ Max 19.2 1 0.55 x t1 0.55 x t1 Units MHz s ns ns 5 5 1 40 ns ns tCLK ns tCLK tCLK ns ns ns ns ns tCLK tCLK ns ns ns ns ns ns tCLK ns ns tCLK
5 5 12 tCLK + t2 20 20
IOL 1.6mA TO OUTPUT PIN
+1.6V CL 50pF IOH 200 A
Figure 1. Load Circuit for Timing Specifications
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AD7723
t5
CLKIN 2.3V 0.8V
t4
t2 t3
t1 t6
FSI
t7
t8 t9
SCO
t9 t10
Figure 2. Serial Mode Timing for Clock Input, Frame Sync Input and Serial Clock Output
32 CLKIN CYCLES CLKIN
t8
FSI (SFMT = 1)
t14
SCO (CFMT = 0)
t11
FSO (SFMT = 0)
t12
FSO (SFMT = 1)
t11
t13
SDO D15 D14 D13 D2 D1 D0 D15 D14
Figure 3. Serial Mode 1. Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output and Serial Data Output (Refer to Table I for Control Inputs, TSI = DOE)
32 CLKIN CYCLES
CLKIN
t8
FSI
t14
SCO (CFMT = 0)
t11
FSO
t12
t13
SDO D2 D1 D0 D15 D14 D13 D12 D11 D5 D4 D3 D2 D1 D0 D15 D14
Figure 4. Serial Mode 2. Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output and Serial Data Output (Refer to Table I for Control Inputs, TSI = DOE)
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AD7723
16 CLKIN CYCLES CLKIN
t8
FSI
t14
SCO (CFMT = 0)
t11
FSO
t12
t13
SDO D2 D1 D0 D15 D14 D13 D12 D11 D5 D4 D3 D2 D1 D0 D15 D14
Figure 5. Serial Mode 3. Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output and Serial Data Output (Refer to Table I for Control Inputs, TSI = DOE)
Table I. Serial Interface (Mode1 = 0, Mode2 = 0)
Serial Mode 1 1 2 2 3
Decimation Digital Filter Ratio (SLDR) Mode (SLP) 32 32 32 32 16 Low Pass Band Pass Low Pass Band Pass Low Pass
SCO Frequency Output Data (SCR) Rate fCLKIN fCLKIN fCLKIN/2 fCLKIN/2 fCLKIN fCLKIN/32 fCLKIN/32 fCLKIN/32 fCLKIN/32 fCLKIN/16
Control Inputs SLDR SLP SCR 1 1 1 1 0 1 0 1 0 1 0 0 1 1 0
Table II. Parallel Interface Digital Filter Decimation Mode Ratio Output Data Rate Control Inputs MODE1 MODE2
Band Pass Low Pass Low Pass
32 32 16
fCLKIN/32 fCLKIN/32 fCLKIN/16
0 1 1
1 0 1
DOE
t15
SDO
t16
Figure 6. Serial Mode Timing for Data Output Enable and Serial Data Output
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t18
CLKIN
t19 t17
DRDY
t19
t20
DB0-DB15
WORD N - 1
WORD N
WORD N + 1
Figure 7a. Parallel Mode Read Timing, CS and RD Tied Logic Low
CLKIN
t18 t19
DRDY
t22
t19
RD/CS
t21 t21
DB0-DB15
t22 t24
VALID DATA
t23
Figure 7b. Parallel Mode Read Timing, CS = RD
t28 CLKIN
t26 SYNC t25
DRDY t27
Figure 8. SYNC Timing
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AD7723
ABSOLUTE MAXIMUM RATINGS*
(TA = +25C unless otherwise noted)
ORDERING GUIDE
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V AVDD , AVDD1 to AGND . . . . . . . . . . . . . . . . . -0.3 V to +7 V AVDD , AVDD1 to DVDD . . . . . . . . . . . . . . . . . . . -1 V to +1 V AGND, AGND1 to DGND . . . . . . . . . . . . -0.3 V to +0.3 V Digital Inputs to DGND . . . . . . . . . -0.3 V to DVDD + 0.3 V Digital Outputs to DGND . . . . . . . . -0.3 V to DVDD + 0.3 V VIN(+), VIN(-) to AGND . . . . . . . . -0.3 V to AVDD + 0.3 V REF1 to AGND . . . . . . . . . . . . . . . . -0.3 V to AVDD + 0.3 V REF2 to AGND . . . . . . . . . . . . . . . . -0.3 V to AVDD + 0.3 V Operating Temperature Range . . . . . . . . . . - 40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150C JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 95C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Model
Temperature Range
Package Description
Package Option
AD7723BS -40C to +85C Plastic Quad Flatpack S-44
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7723 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION 44-Lead PQFP Package
DGND/DB3 SLDR/DB12 33 SCR/DB13
PIN 1 IDENTIFIER
SFMT/DB5
44 43 42 41 40 39 38 37 36 35 34 DGND/DB2 1 DGND/DB1 2 DGND/DB0 3 CFMT/RD 4 DGND/DRDY 5 DGND 6 MODE2 7 MODE1 AGND1 8 9
SLP/DB11
SCO/DB7
DOE/DB4
SDO/DB8
FSO/DB9
FSI/DB6
DVDD
TSI/DB10
32 DGND/DB14 31 DGND/DB15 30 DVDD/CS
AD7723
TOP VIEW (Not to Scale)
29 SYNC 28 DGND 27 STBY 26 AVDD 25 AGND 24 UNI 23 REF2
AGND1 10 AVDD1 11 12 13 14 15 16 17 18 19 20 21 22 REF1 HALF_PWR XTAL_OFF AGND2 XTAL VIN(-) CLKIN AGND AGND VIN(+) AVDD
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PIN FUNCTION DESCRIPTIONS
Mnemonic AVDD1 AGND1 AVDD AGND AGND2 DVDD DGND REF1 REF2
Pin No. 11 9, 10 17, 26 16, 18, 25 22 39 6, 28 21 23
Description Digital Logic Power Supply Voltage for the Analog Modulator. Digital Logic Power Supply Ground for the Analog Modulator. Positive Power Supply Voltage for the Analog Modulator. Power Supply Ground for the Analog Modulator. Power Supply Ground Return to the Reference Circuitry, REF2, of the Analog Modulator. Digital Power Supply Voltage; +5 V 5%. Ground Reference for Digital Circuitry. Reference Output. REF1 connects through 3 k to the output of the internal 2.5 V reference and to a buffer amplifier that drives the - modulator. Reference Input. REF2 connects to the output of an internal buffer amplifier that drives the - modulator. When REF2 is used as an input, REF1 must be connected to AGND to disable the internal buffer amplifier. Positive Terminal of the Differential Analog Input. Negative Terminal of the Differential Analog Input. Analog Input Range Select Input. The UNI pin selects the analog input range for either bipolar or unipolar operation. A logic high input selects unipolar operation and a logic low selects bipolar operation. Clock Input. An external clock source can be applied directly to this pin with XTAL_OFF tied high. Alternatively, a parallel resonant fundamental frequency crystal, in parallel with a 1 M resistor can be connected between the XTAL pin and the CLKIN pin with XTAL_OFF tied low. External capacitors are then required from the CLKIN and XTAL pins to ground. Consult the crystal manufacturer's recommendation for the load capacitors. Input to Crystal Oscillator Amplifier. If an external clock is used, XTAL should be tied to AGND1. Oscillator Enable Input. A logic high disables the crystal oscillator amplifier to allow use of an external clock source. Set low when using an external crystal between the CLKIN and XTAL pins. Mode Control Inputs. The MODE1 and MODE2 pins choose either parallel or serial data interface operation and select the operating mode for the digital filter in parallel mode. Refer to Tables I and II. When set high, the power dissipation is reduced by approximately one-half and a maximum CLKIN frequency of 10 MHz applies. Synchronization Logic Input. When using more than one AD7723, operated from a common master clock, SYNC allows each ADC to simultaneously sample its analog input and update its output register. A rising edge resets the AD7723 digital filter sequencer counter to zero. When the rising edge of CLKIN senses a logic low on SYNC, the reset state is released. Because the digital filter and sequencer are completely reset during this action, SYNC pulses cannot be applied continuously. Standby Logic Input. A logic high sets the AD7723 into the power-down state.
VIN(+) VIN(-) UNI CLKIN
20 19 24 12
XTAL XTAL_OFF MODE1/2 HALF_PWR SYNC
13 14 8, 7 15 29
STBY
27
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AD7723
PARALLEL MODE PIN FUNCTION DESCRIPTIONS
Mnemonic DVDD/CS CFMT/RD
Pin No. 30 4
Description Chip Select Logic Input. Read Logic Input. Used in conjunction with CS to read data from the parallel bus. The output data bus is enabled when the rising edge of CLKIN senses a logic low level on RD if CS is also low. When RD is sensed high, the output data bits, DB15-DB0 will be high impedance. Data Ready Logic Output. A falling edge indicates a new output word is available to be read from the output data register. DRDY will return high upon completion of a read operation. If a read operation does not occur between output updates, DRDY will pulse high for two CLKIN cycles before the next output update. DRDY also indicates when conversion results are available after a SYNC sequence. Data Output Bit, (MSB) Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit. Data Output Bit, (LSB).
DGND/DRDY
5
DGND/DB15 DGND/DB14 SCR/DB13 SLDR/DB12 SLP/DB11 TSI/DB10 FSO/DB9 SDO/DB8 SCO/DB7 FSI/DB6 SFMT/DB5 DOE/DB4 DGND/DB3 DGND/DB2 DGND/DB1 DGND/DB0
31 32 33 34 35 36 37 38 40 41 42 43 44 1 2 3
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SERIAL MODE PIN FUNCTION DESCRIPTIONS
Mnemonic CFMT/RD
Pin No. 4
Description Serial Clock Format Logic Input. The clock format pin selects whether the serial data, SDO, is valid on the rising or falling edge of the serial clock, SCO. When CFMT is logic low, serial data is valid on the falling edge of the serial clock, SCO. If CFMT is logic high, SDO is valid on the rising edge of SCO. Data Output Enable Logic Input. The DOE pin controls the three-state output buffer of the SDO pin. The active state of DOE is determined by the logic level on the TSI pin. When the DOE logic level equals the level on the TSI pin the serial data output, SDO, is active. Otherwise SDO will be high impedance. SDO can be three-state after a serial data transmission by connecting DOE to FSO. In normal operations, TSI and DOE should be tied low. Serial Data Format Logic Input. The logic level on the SFMT pin selects the format of the FSO signal for Serial Mode 1. A logic low makes the FSO output a pulse, one SCO cycle wide at the beginning of a serial data transmission. With SFMT set to a logic high, the FSO signal is a frame pulse that is active low for the duration of the 16-bit transmission. For Serial Modes 2 and 3, SFMT should be tied high. Frame Synchronization Logic Input. The FSI input is used to synchronize the AD7723 serial output data register to an external source and to allow more than one AD7723, operated from a common master clock, to simultaneously sample its analog input and update its output register. Serial Clock Output. Serial Data Output. The serial data is shifted out MSB first, synchronous with the SCO. Serial Mode 1 data transmissions last 32 SCO cycles. After the LSB is output, trailing zeros are output for the remaining 16 SCO cycles. Serial Modes 2 and 3 data transmissions last 16 SCO cycles. Frame Sync Output. FSO indicates the beginning of a word transmission on the SDO pin. Depending on the logic level of the SFMT pin, the FSO signal is either a positive pulse approximately one SCO period wide, or a frame pulse which is active low for the duration of the 16-data bit transmission. Time Slot Logic Input. The logic level on TSI sets the active state of the DOE pin. With TSI set logic high, DOE will enable the SDO output buffer when it is a logic high, and vice versa. TSI is used when two AD7723s are connected to the same serial data bus. When this function is not needed, TSI and DOE should be tied low. Serial Mode Low Pass/Band Pass Filter Select Input. With SLP set logic high, the low-pass filter response is selected. A logic low selects band pass. Serial Mode Low/High Output Data Rate Select Input. With SLDR set logic high, the low data rate is selected. A logic low selects the high data rate. The high data rate corresponds to data at the output of the fourth decimation filter (Decimate by 16). The low data rate corresponds to data at the output of the fifth decimation filter (Decimate by 32). Serial Clock Rate Select Input. With SCR set logic low, the serial clock output frequency, SCO, is equal to the CLKIN frequency. A logic high sets it equal to one-half the CLKIN frequency. Tie to DVDD . Tie to DGND. Tie to DGND. Tie to DGND. Tie to DGND. Tie to DGND. Tie to DGND. Tie to DGND.
DOE/DB4
43
SFMT/DB5
42
FSI/DB6
41
SCO/DB7 SDO/DB8
40 38
FSO/DB9
37
TSI/DB10
36
SLP/DB11 SLDR/DB12
35 34
SCR/DB13 DVDD/CS DGND/DB14 DGND/DB15 DGND/DRDY DGND/DB0 DGND/DB1 DGND/DB2 DGND/DB3
33 30 32 31 5 3 2 1 44
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AD7723
TERMINOLOGY Signal-to-Noise Ratio (SNR) Integral Nonlinearity
SNR is the measured signal-to-noise ratio at the output of the ADC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all of the nonfundamental signals up to half the output data rate (FO/2), excluding dc. The ADC is evaluated by applying a low noise, low distortion sine wave signal to the input pins. By generating a Fast Fourier Transform (FFT) plot, the SNR data can then be obtained from the output spectrum.
Total Harmonic Distortion (THD)
This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are minus full scale, a point 0.5 LSB below the first code transition (100 . . . 00 to 100 . . . 01 in bipolar mode, 000 . . . 00 to 000 . . . 01 in unipolar mode) and plus full scale, a point 0.5 LSB above the last code transition (011 . . . 10 to 011 . . . 11 in bipolar mode, 111 . . . 10 to 111 . . . 11 in unipolar mode). The error is expressed in LSBs.
Differential Nonlinearity
THD is the ratio of the rms sum of the harmonics to the rms value of the fundamental. THD is defined as: V 2 +V 3 +V 4 +V 5 +V 6 THD = 20 log V1
2 2 2 2 2
This is the difference between the measured and the ideal 1 LSB change between two adjacent codes in the ADC.
Common-Mode Rejection Ratio
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through sixth harmonics. The THD is also derived from the FFT plot of the ADC output spectrum.
Spurious Free Dynamic Range (SFDR)
The ability of a device to reject the effect of a voltage applied to both input terminals simultaneously--often through variation of a ground level--is specified as a common-mode rejection ratio. CMRR is the ratio of gain for the differential signal to the gain for the common-mode signal.
Unipolar Offset Error
Defined as the difference, in dB, between the peak spurious or harmonic component in the ADC output spectrum (up to FO /2 and excluding dc) and the rms value of the fundamental. Normally, the value of this specification will be determined by the largest harmonic in the output spectrum of the FFT. For input signals whose second harmonics occur in the stop band region of the digital filter, the spur in the noise floor limits the SFDR.
Passband Ripple
Unipolar offset error is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal differential voltage (VIN(+) - VIN(-)+ 0.5 LSB) when operating in the unipolar mode.
Bipolar Offset Error
This is the deviation of the midscale transition code (111 . . . 11 to 000 . . . 00) from the ideal differential voltage (VIN(+) - VIN(-) - 0.5 LSB) when operating in the bipolar mode.
Gain Error
The frequency response variation of the AD7723 in the defined passband frequency range.
Passband Frequency
The first code transition should occur at an analog value 1/2 LSB above -full scale. The last transition should occur for an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.
The frequency up to which the frequency response variation is within the passband ripple specification.
Cutoff Frequency
The frequency below which the AD7723's frequency response will not have more than 3 dB of attenuation.
Stopband Frequency
The frequency above which the AD7723's frequency response will be within its stopband attenuation.
Stopband Attenuation
The AD7723's frequency response will not have less than 90 dB of attenuation in the stated frequency band.
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Typical Performance Characteristics- AD7723
(AVDD = DVDD = 5 V; TA = +25 C; CLKIN = 19.2 MHz; External +2.5 V Reference, unless otherwise noted)
110 SIGNAL FREQUENCY = 98kHz MEASUREMENT BANDWIDTH = 460kHz 100 102 90 THD 80 dB SFDR 70 SNR 60 92 50 40 -28 SNR 90 88 -50 dB 100 98 96 94 THD 106 104 SIGNAL FREQUENCY = 98kHz MEASUREMENT BANDWIDTH = 300kHz 3RD
2ND
-23
-18 -13 -8 ANALOG INPUT LEVEL - dB
-3
2
-25
0 25 50 TEMPERATURE - C
75
100
Figure 9. SNR, THD and SFDR vs. Analog Input Level Relative to Full Scale (Output Data Rate = 1.2 MHz)
Figure 12. SNR and THD vs. Temperature (Output Data Rate = 600 kHz)
110 SIGNAL FREQUENCY = 98kHz MEASUREMENT BANDWIDTH = 300kHz 100 90 THD 80 dB SFDR 70 SNR 60 50 dB
106 104 102 100 98 96 94 92 90 88 86 SNR INPUT SIGNAL = 10kHz MEASUREMENT BANDWIDTH = 0.383 OWR THD SFDR
40 -28
-23
-18 -13 -8 ANALOG INPUT LEVEL - dB
-3
2
84 100
500
1000 1500 OUTPUT WORD RATE - kHz
2150
Figure 10. SNR, THD and SFDR vs. Analog Input Level Relative to Full Scale (Output Data Rate = 600 kHz)
Figure 13. SNR, THD and SFDR vs. Sampling Frequency (Decimate by 16)
102 100 98 96 94 dB
SIGNAL FREQUENCY = 98kHz MEASUREMENT BANDWIDTH = 460kHz 3RD
115 INPUT SIGNAL = 10kHz MEASUREMENT BANDWIDTH = 0.5 110 SFDR OWR
2ND 105 THD dB 100
92 90 88 SNR 86 84 -50 90 50 150 450 300 600 OUTPUT WORD RATE - kHz 750 900 95 SNR -25 0 25 50 TEMPERATURE - C 75 100 THD
Figure 11. SNR and THD vs. Temperature (Output Data Rate = 1.2 MHz)
Figure 14. SNR, THD and SFDR vs. Sampling Frequency (Decimate by 32)
REV. 0
-13-
AD7723
2000 1800 FREQUENCY OF OCCURRENCE 1600 DNL ERROR - LSB 1400 1200 1000 800 600 400 200 0 32700 32702 32704 32706 32708 CODE 32710 32712 32713 VIN(+) = VIN(-) 8192 SAMPLES TAKEN
1.00 0.80 0.60 0.40 0.20 0.00 -0.20 -0.40 -0.60 -0.80 -1.00 0 16384 32768 CODE 49152 65535 67108864 SAMPLES TAKEN DIFFERENTIAL MODE
Figure 15. Histogram of Output Codes with DC Input (Output Data Rate = 1.2 MHz)
Figure 18. Differential Nonlinearity (Output Data Rate = 600 kHz)
5000 4500 FREQUENCY OF OCCURRENCE 4000 3500 3000 2500 2000 1500 1000 500 0 32703 32704 32705 32706 32707 CODE 32708 32709 32710 INL ERROR - LSB VIN(+) = VIN(-) 8192 SAMPLES TAKEN
1.00 0.80 0.60 0.40 0.20 0.00 -0.20 -0.40 -0.60 -0.80 -1.00 0 16384 32768 CODE 49152 65535 67108864 SAMPLES TAKEN DIFFERENTIAL MODE
Figure 16. Histogram of Output Codes with DC Input (Output Data Rate = 600 kHz)
Figure 19. Integral Nonlinearity (Output Data Rate = 1.2 MHz)
1.00 0.80 0.60 DNL ERROR - LSB 0.40 0.20 0.00 -0.20 -0.40 -0.60 -0.80 -1.00 0 16384 32768 CODE 49152 65535 INL ERROR - LSB 67108864 SAMPLES TAKEN DIFFERENTIAL MODE
1.00 0.80 0.60 0.40 0.20 0.00 -0.20 -0.40 -0.60 -0.80 -1.00 0 16384 32768 CODE 49152 65535 67108864 SAMPLES TAKEN DIFFERENTIAL MODE
Figure 17. Differential Nonlinearity (Output Data Rate = 1.2 MHz)
Figure 20. Integral Nonlinearity (Output Data Rate = 600 kHz)
-14-
REV. 0
AD7723
225 200 AIDD (HALF_POWER = 0) 175 150 POWER - mW 125 100 75 50 25 0 0 5 10 15 CLOCK FREQUENCY - MHz 20 25 AIDD (HALF_POWER = 1) DIDD
quantization noise, a high order modulator is employed to shape the noise spectrum, so that most of the noise energy is shifted out of the band of interest (Figure 24b). The digital filter that follows the modulator removes the large out-of-band quantization noise, (Figure 24c) while also reducing the data rate from fCLKIN at the input of the filter to fCLKIN/32 or fCLKIN/16 at the output of the filter, depending on the state on the MODE1/2 pins in parallel interface mode or the pin SLDR in serial interface mode. The AD7723 output data rate is a little over twice the signal bandwidth, which guarantees that there is no loss of data in the signal band. Digital filtering has certain advantages over analog filtering. Firstly, since digital filtering occurs after the A/D conversion, it can remove noise injected during the conversion process. Analog filtering cannot remove noise injected during conversion. Secondly, the digital filter combines low passband ripple with a steep roll-off, while also maintaining a linear phase response.
Figure 21. Power Consumption vs. CLKIN Frequency
0 SNR = -86.19dB SNR&D = -85.9dB THD = -96.42dB SFDR = -99.61dB 2ND HARMONIC = -100.98dB 3RD HARMONIC = -99.61dB AIN = 100kHz MEASURED BW = 460kHz
POWER LEVEL RELATIVE TO FULL SCALE - dB
-25
QUANTIZATION NOISE BAND OF INTEREST fCLKIN/2
-50
(a)
-75
-100
NOISE SHAPING
-125
BAND OF INTEREST
fCLKIN/2
(b)
-150 0E+0 100E+3 200E+3 300E+3 400E+3 FREQUENCY - Hz 500E+3 600E+3 DIGITAL FILTER CUTOFF FREQUENCY
Figure 22. 16K Point FFT (Output Data Rate = 1.2 MHz)
0 POWER LEVEL RELATIVE TO FULL SCALE - dB -20 -40 -60 -80 -100 -120 -140 -160 0E+0 SNR = -89.91dB SNR&D = -89.7dB THD = -101.16dB SFDR = -102.1dB 2ND HARMONIC = -102.1dB 3RD HARMONIC = -110.3dB AIN = 50kHz MEASURED BW = 300kHz
BAND OF INTEREST
fCLKIN/2
(c) Figure 24. Sigma-Delta ADC
50E+3
200E+3 100E+3 150E+3 FREQUENCY - Hz
250E+3
300E+3
Figure 23. 16K Point FFT (Output Data Rate = 600 kHz)
CIRCUIT DESCRIPTION
The AD7723 ADC employs a sigma-delta conversion technique to convert the analog input into an equivalent digital word. The modulator samples the input waveform and outputs an equivalent digital word at the input clock frequency, fCLKIN. Due to the high oversampling rate, which spreads the quantization noise from 0 to fCLKIN/2, the noise energy contained in the band of interest is reduced (Figure 24a). To further reduce the REV. 0
The AD7723 employs four or five Finite Impulse Response (FIR) filters in series. Each individual filter's output data rate is half that of the filter's input data rate. When data is fed to the interface from the output of the fourth filter, the output data rate is fCLKIN/16 and the resulting Over Sampling Ratio (OSR) of the converter is 16. Data fed to the interface from the output of the fifth filter results in an output data rate of fCLKIN/32 and a corresponding OSR for the converter of 32. When an Output Data Rate (ODR) of fCLKIN/32 is selected, the digital filter response can be set to either low-pass or band-pass. The bandpass response is useful when the input signal is band limited since the resulting output data rate is half that required to convert the band when the low pass operating mode is used. To illustrate the operation of this mode, consider a band-limited signal as shown in Figure 25a. This signal band can be correctly converted by selecting the (low pass) ODR = fCLKIN/16 mode, as shown in Figure 25b. Note that the output data rate is a little over twice the maximum frequency in the frequency band. Alternatively the band-pass mode can be selected as shown in Figure 25c. The band-pass filter removes unwanted signals from dc to just below fCLKIN/64. Rather than outputting data at fCLKIN/16, the output of the band-pass filter is sampled at fCLKIN/32. This
-15-
AD7723
effectively translates the wanted band to a maximum frequency of a little less than fCLKIN/64 as shown in Figure 25d. Halving the output data rate reduces the work load of any following signal processor and also allows a lower serial clock rate to be used.
BAND LIMITED SIGNAL 0dB 0dB
-100dB
(a)
LOW PASS FILTER RESPONSE 0dB SAMPLE IMAGE
fCLKIN/16
ODR 0.0 0.5 fCLKIN 1.0
fCLKIN/16 LOW PASS FILTER. OUTPUT DATA RATE = fCLKIN/16
Figure 26b. Low-Pass Filter Decimate by 32
(b)
BAND-PASS FILTER RESPONSE 0dB SAMPLE IMAGE 0dB
BAND-PASS FILTER.
fCLKIN/16
-100dB
(c)
FREQUENCY TRANSLATED INPUT SIGNAL ODR SAMPLE IMAGE
0dB
fCLKIN/16 LOW PASS FILTER. OUTPUT DATA RATE = fCLKIN/32 0.0
(d) Figure 25. Band-Pass Operation
0.5 fCLKIN
1.0
Figure 26c. Band-Pass Filter Decimate by 32
The frequency response of the three digital filter operating modes is shown in Figures 26a, 26b, and 26c.
0dB
-100dB
Figure 27a shows the frequency response of the digital filter in both low-pass and band-pass modes. Due to the sampling nature of the converter, the pass-band response is repeated about the input sampling frequency, fCLKIN and at integer multiples of fCLKIN. Out-of-band noise or signals coincident with any of the filter images are aliased down to the passband. However, due to the AD7723's high oversampling ratio, these bands occupy only a small fraction of the spectrum, and most broadband noise is attenuated by at least 90 dB. In addition, as shown in Figure 27b, with even a low order filter, there is significant attenuation at the first image frequency. This contrasts with a normal Nyquist rate converter where a very high order antialias filter is required to allow most of the band width to be used while ensuring sufficient attenuation at multiples of fCLKIN.
0dB
0.0
0.5 fCLKIN
1.0
1fCLKIN
2fCLKIN
3fCLKIN
Figure 27a. Digital Filter Frequency Response
OUTPUT DATA RATE ANTIALIAS FILTER RESPONSE 0dB
Figure 26a. Low-Pass Filter Decimate by 16
REQUIRED ATTENUATION fCLKIN
fCLKIN/32
Figure 27b. Frequency Response of Antialias Filter
-16-
REV. 0
AD7723
APPLYING THE AD7723 Analog Input Range
while also settling to the required accuracy by the end of each half-clock phase.
A 500 VIN(+) B A VIN(-) 500 B CLKIN
A B A
The AD7723 has differential inputs to provide common-mode noise rejection. In unipolar mode the analog input range is 0 to 8/5 x V REF2, while in bipolar mode the analog input range is 4/5 x VREF2. The output code is twos complement binary in both modes with 1 LSB = 61 V. The ideal input/output transfer characteristics for the two modes are shown in Figure 28 below. In both modes the absolute voltage on each input must remain within the supply range AGND to AVDD. The bipolar mode allows either single-ended or complementary input signals.
011...111 011...110
AD7723
2pF 2pF
AC GROUND
B
Figure 30. Analog Input Equivalent Circuit
Driving the Analog Inputs
000...010 000...001 000...000 111...111 111...110
100...001 100...000 -4/5 VREF2 (0V) (+4/5 0V VREF2) +4/5 (+8/5 VREF2 - 1LSB BIPOLAR VREF2 - 1LSB) UNIPOLAR
To interface the signal source to the AD7723, at least one op amp will generally be required. Choice of op amp will be critical to achieving the full performance of the AD7723. The op amp not only has to recover from the transient loads that the ADC imposes on it, but must also have good distortion characteristics and very low input noise. Resistors in the signal path will also add to the overall thermal noise floor, necessitating the choice of low value resistors. Placing an RC filter between the drive source and the ADC inputs, as shown in Figure 31, has a number of beneficial affects: transients on the op amp outputs are significantly reduced since the external capacitor now supplies the instantaneous charge required when the sampling capacitors are switched to the ADC input pins and, input circuit noise at the sample images is now significantly attenuated resulting in improved overall SNR. The external resistor serves to isolate the external capacitor from the ADC output, thus improving op amp stability while also isolating the op amp output from any remaining transients on the capacitor. By experimenting with different filter values, the optimum performance can be achieved for each application. As a guideline, the RC time constant (R x C) should be less than a quarter of the clock period to avoid nonlinear currents from the ADC inputs being stored on the external capacitor and degrading distortion. This restriction means that this filter cannot form the main antialias filter for the ADC.
R VIN(+) C R VREF = 2.5V VIN(-)
Figure 28. Bipolar (Unipolar) Mode Transfer Function
The AD7723 will accept full-scale inband signals, however, large scale out of band signals can overload the modulator inputs. Figure 29 shows the maximum input signal level as a function of frequency. A minimal single-pole RC antialias filter set to fCLKIN/24 will allow full-scale input signals over the entire frequency spectrum.
2.200 2.100 2.000 PEAK INPUT - V pk 1.900 1.800 1.700 1.600 1.500 1.400 1.300 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 INPUT SIGNAL FREQUENCY RELATIVE TO fCLKIN 0.5
AD7723
Figure 31. Input RC Network
Figure 29. Peak Input Signal Level vs. Signal Frequency
Analog Input
The analog input of the AD7723 uses a switched capacitor technique to sample the input signal. For the purpose of driving the AD7723, an equivalent circuit of the analog inputs is shown in Figure 30. For each half clock cycle, two highly linear sampling capacitors are switched to both inputs, converting the input signal into an equivalent sampled charge. A signal source driving the analog inputs must be able to source this charge, REV. 0
With the unipolar input mode selected, just one op amp is required to buffer single ended input signals. However, driving the AD7723 with complementary signals and with the bipolar input range selected has some distinct advantages: even order harmonics in both the drive circuits and the AD7723 front end are attenuated; and the peak to peak input signal range on both inputs is halved. Halving the input signal range allows some op amps to be powered from the same supplies as the AD7723. Although a complementary driver will require the use of two op amps per ADC, it may avoid the need to generate additional supplies just for these op amps. -17-
AD7723
Figures 32 and 33 show two such circuits for driving the AD7723. Figure 32 is intended for use when the input signal is biased about 2.5 V while Figure 33 is used when the input signal is biased about ground. While both circuits convert the input signal into a complementary signal, the circuit in Figure 33 also level shifts the signal so that both outputs are biased about 2.5 V. Suitable op amps include the AD8047, AD8044, AD8041 and its dual equivalent the AD8042. The AD8047 has lower input noise than the AD8041/42 but has to be supplied from a +7.5 V/ -2.5 V supply. The AD8041/AD8042 will typically degrade SNR from 90 dB to 88 dB but can be powered from the same single +5 V supply as the AD7723.
RFB 220 AIN = 2V BIASED ABOUT 2.5V RSOURCE RIN 390 50 AD8047 A1
modulator's switched cap DAC (REF2). When using the internal reference a 1 F capacitor is required between REF1 and AGND to decouple the bandgap noise. If the internal reference is required to bias external circuits, use an external precision op amp to buffer REF1.
1V
COMPARATOR
AD7723
REF1 1F 3k
REFERENCE BUFFER SWITCHED-CAP DAC REFERENCED 2.5V REFERENCE
REF2
27 VIN(+)
Figure 34. Reference Circuit Block Diagram
220 220pF 220 27 10k A2 AD8047 220nF 10nF REF1 1F GAIN = 2 RFB/(RSOURCE + RIN) VIN(-) REF2
AD7723
Where gain error or gain error drift requires the use of an external reference, the reference buffer in Figure 34 can be turned off by grounding the REF1 pin and the external reference can be applied directly to pin REF2. The AD7723 will accept an external reference voltage between 1.2 V to 3.15 V. By applying a 3 V rather than a 2.5 V reference, SNR is typically improved by about 1 dB. Where the output common-mode range of the amplifier driving the inputs is restricted, the full-scale input signal span can be reduced by applying a lower than 2.5 V reference. For example, a 1.25 V reference would make the bipolar input span 1 V, but would degrade SNR. In all cases, since the REF2 voltage connects to the analog modulator, a 220 nF and 10 nF capacitor must connect directly from REF2 to AGND. The external capacitor provides the charge required for the dynamic load presented at the REF2 pin (See Figure 35).
Figure 32. Single-Ended to Differential Input Circuit for Bipolar Mode Operation (Analog Input Biased About +2.5 V)
RFB 220 AD8047 27 A1 RBALANCE2 220 RBALANCE2 220 RREF1 10k RREF2 20k 27 A2 AD8047 220nF 10nF REF1 GAIN = 2 RFB/(RIN + RSOURCE) RBALANCE1 = RBALANCE2 (RIN + RSOURCE)/(2 RREF2 = RREF1 (RIN + RSOURCE)/RFB 1F RFB) VIN(-) REF2 VIN(+)
AIN = 2V BIASED ABOUT GROUND
RSOURCE RIN 390 50
A RBALANCE1 220 REF2 220pF 4pF B
AD7723
220nF
10nF B
4pF
A
SWITCHED-CAP DAC REFERENCED CLKIN A B A B
Figure 35. REF2 Equivalent Input Circuit
The AD780 is ideal to use as an external reference with the AD7723. Figure 36 shows a suggested connection diagram. Grounding Pin 8 on the AD780 selects the 3 V output mode.
+5V O/P 8 SELECT 2 +VIN NC 7
1 NC 3 TEMP
Figure 33. Single-Ended to Differential Input Circuit for Bipolar Mode Operation (Analog Input Biased About Ground)
Applying the Reference
2.5V
REF2
The reference circuitry used in the AD7723 includes an on-chip 2.5 V bandgap reference and a reference buffer circuit. The block diagram of the reference circuit is shown in Figure 34. The internal reference voltage is connected to REF1 through a 3 k resistor and is internally buffered to drive the analog
1F 22nF
VOUT 6
220nF 22 F
10nF
AD7723
REF1
4 GND
TRIM 5 AD780
NC = NO CONNECT
Figure 36. External Reference Circuit Connection
-18-
REV. 0
AD7723
Clock Generation
The AD7723 contains an oscillator circuit to allow a crystal or an external clock signal to generate the master clock for the ADC. The connection diagram for use with a crystal is shown in Figure 37. Consult the manufacturer's recommendation for the load capacitors. To enable the oscillator circuit on board the AD7723, XTAL_OFF should be tied low.
AD7723
XTAL 1M CLKIN
applied synchronous to the falling edge of CLKIN. This way, on the next rising edge of CLKIN, SYNC is sensed low, the filter is taken out of its reset state and multiple parts begin to gather input samples. Following a SYNC, the modulator and filter need time to settle before data can be read from the AD7723. DRDY goes high following a synchronization and it remains high until valid data is available at the interface.
DATA INTERFACING
Figure 37. Crystal Oscillator Connection
When an external clock source is being used, the internal oscillator circuit can be disabled by tying XTAL_OFF high. A low phase noise clock should be used to generate the ADC sampling clock because sampling clock jitter effectively modulates the input signal and raises the noise floor. The sampling clock generator should be isolated from noisy digital circuits, grounded and heavily decoupled to the analog ground plane. The sampling clock generator should be referenced to the analog ground in a split ground system. However, this is not always possible because of system constraints. In many applications, the sampling clock must be derived from a higher frequency multipurpose system clock that is generated on the digital ground plane. If the clock signal is passed between its origin on a digital ground plane to the AD7723 on the analog ground plane, the ground noise between the two planes adds directly to the clock and will produce excess jitter. The jitter can cause degradation in the signal-to-noise ratio and also produce unwanted harmonics. This can be remedied somewhat by transmitting the sampling signal as a differential one, using either a small RF transformer or a high speed differential driver and a receiver such as PECL. In either case, the original master system clock should be generated from a low phase noise crystal oscillator.
SYSTEM SYNCHRONIZATION
The AD7723 offers a choice of serial or parallel data interface options to meet the requirements of a variety of system configurations. In parallel mode, multiple AD7723s can easily be configured to share a common data bus. Serial mode is ideal when it is required to minimize the number of data interface lines connected to a host processor. In either case, careful attention to the system configuration is required to realize the high dynamic range available with the AD7723. Consult the recommendation in the Layout and Grounding section. The following recommendations for parallel interfacing also apply for the system design when using the serial mode.
Parallel Interface
When using the AD7723, place a buffer/latch adjacent to the converter to isolate the converter's data lines from any noise which may be on the data bus. Even though the AD7723 has three state outputs, use of an isolation latch represents good design practice. Figure 38 shows how the parallel interface of the AD7723 can be configured to interface with the system data bus of a microprocessor or a microcontroller such as the MC68HC16 or 8XC251. With CS and RD tied permanently low, the data output bits are always active. When DRDY goes high for two clock cycles, the rising edge of DRDY is used to latch the conversion data before a new conversion result is loaded into the output data register. The falling edge of DRDY then sends an appropriate interrupt signal for interface control. Alternatively, if buffers are used instead of latches, the falling edge of DRDY provides the necessary interrupt when a new output word is available from the AD7723.
DSP 16 74XX16374 16 D0-15
AD7723
DB0-15
The SYNC input provides a synchronization function for use in parallel or serial mode. SYNC allows the user to begin gathering samples of the analog input from a known point in time. This allows a system using multiple AD7723s, operated from a common master clock, to be synchronized so that each ADC simultaneously updates its output register. In a system using multiple AD7723s, a common signal to their sync inputs will synchronize their operation. On the rising edge of SYNC, the digital filter sequencer is reset to zero. The filter is held in a reset state until a rising edge on CLKIN senses SYNC low. A SYNC pulse, one CLKIN cycle long, can be
ADDR DECODE DRDY CS RD OE
ADDR
RD
INTERRUPT
Figure 38. Parallel Interface Connection
REV. 0
-19-
AD7723
SERIAL INTERFACE
The AD7723's serial data interface can operate in three modes, depending on the application requirements. The timing diagrams in Figures 3, 4 and 5 show how the AD7723 may be used to transmit its conversion results. Table I shows the control inputs required to select each serial mode, and the digital filter operating mode. The AD7723 operates solely in the master mode providing three serial data output pins for transfer of the conversion results. The serial data clock output, SCO, serial data output, SDO, and frame sync output, FSO, are all synchronous with CLKIN. FSO is continuously output at the conversion rate of the ADC. Serial data shifts out of the SDO pin synchronous with SCO. The FSO is used to frame the output data transmission to an external device. An output data transmission is either 16 or 32 SCO cycles in duration (refer to Table I). Serial data shifts out of the SDO pin, MSB first, LSB last, for a duration of 16 SCO cycles. In Serial Mode 1, SDO outputs zeros for the last 16 SCO cycles of the 32-cycle data transmission frame. The clock format pin, CFMT, selects the active edge of SCO. With CFMT tied logic low, the serial interface outputs FSO and SDO change state on the SCO rising edge and are valid on the falling edge of SCO. With CFMT set high, FSO and SDO change state on the falling SCO edge and are valid on the SCO rising edge. The Frame Sync Input, FSI, can be used if the AD7723 conversion process must be synchronized to an external source. FSI allows the conversion data presented to the serial interface to be a filtered and decimated result derived from a known point in time. A common frame sync signal can be applied to two or more AD7723s to synchronize them to a common master clock. When FSI is applied for the first time, the digital filter sequencer counter is reset to zero, the AD7723 interrupts the current data transmission, reloads the output shift register, resets SCO and transmits the conversion result. Synchronization starts immediately and the following conversions are invalid while the digital filter settles. FSI can be applied once after power-up, or it can be a periodic signal, synchronous to CLKIN, occurring every 32 CLKIN cycles. Subsequent FSI inputs applied every 32 CLKIN cycles do not alter the serial data transmission and do not reset the digital filter sequencer counter. FSI is an optional signal; if synchronization is not required, FSI can be tied to a logic low and the AD7723 will generate FSO outputs. In Serial Mode 1, the control input, SFMT, can be used to select the format for the serial data transmission (refer to Figure 3). FSO is either a pulse, approximately one SCO cycle in duration, or a square wave with a period of 32 SCO cycles. With a logic low level on SFMT, FSO pulses high for one SCO cycle at the beginning of a data transmission frame. With a logic high level on SFMT, FSO goes low at the beginning of a data transmission frame and returns high after 16 SCO cycles. Note that in Serial Mode 1, FSI can be used to synchronize the AD7723 if SFMT is set to a logic high. If SFMT is set low, the FSI input will have no effect on synchronization.
In Serial Modes 2 and 3, SFMT should be tied high. TSI and DOE should be tied low in these modes. The FSO is a pulse, approximately one SCO cycle in duration, occurring at the beginning of the serial data transmission.
Two-Channel Multiplexed Operation
Two additional serial interface control pins, DOE and TSI, are provided to allow the serial data outputs of two AD7723s, to easily share one serial data line when operating in Serial Mode 1. Figure 39 shows the connection diagram. Since a serial data transmission frame lasts 32 SCO cycles, two ADCs can share a single data line by alternating transmission of their 16-bit output data onto one SDO pin.
DVDD SFMT CFMT DGND TSI FSI CLKIN FROM CONTROL LOGIC
AD7723
MASTER SDO SCO FSO DOE TO HOST PROCESSOR
AD7723
SLAVE DVDD FSI CLKIN SFMT TSI DGND CFMT DOE SDO SCO FSO
Figure 39. Serial Mode 1 Connection for Two-Channel Multiplexed Operation
The Data Output Enable pin, DOE, controls the SDO output buffer. When the logic level on DOE matches the state of the TSI pin, the SDO output buffer drives the serial data line, otherwise the output of the buffer goes high impedance. The serial format pin, SFMT, is set high to choose the frame sync output format. The clock format pin, CFMT, is set low so that serial data is made available on SDO after the rising edge of SCO and can be latched on the SCO falling edge. The Master device is selected by setting TSI to a logic low and connecting its FSO to DOE. The Slave device is selected with its TSI pin tied high and both its FSI and DOE controlled from the Master's FSO. Since the FSO of the Master controls the DOE input of both the Master and Slave, one ADC's SDO is active while the other is high impedance (Figure 40). When the Master transmits its conversion result during the first 16 SCO cycles of a data transmission frame, the low level on DOE sets the slave's SDO high impedance. Once the Master completes transmitting its conversion data, its FSO goes high, triggers the Slave's FSI to begin its data transmission frame. Since FSO pulses are gated by the release of FSI (going low) and the FSI of the Slave device is held high during its data transmission, the FSO from the Master device must be used for connection to the host processor.
-20-
REV. 0
AD7723
CLKIN
FSI
t9
SCO FSO (MASTER) FSI (SLAVE) DOE (MASTER & SLAVE)
t12
t13
t11
t15
SDO (MASTER) D15 D14 D1 D0
t16
t16
SDO (SLAVE) D1 D0
t15
D15 D14
Figure 40. Serial Mode 1 Timing for Two-Channel Multiplexed Operation
SERIAL INTERFACE TO DSPS
In serial mode, the AD7723 can be directly interfaced to several industry standard digital signal processors. In all cases, the AD7723 operates as the master with the DSP operating as the slave. The AD7723 provides its own serial clock (SCO) to transmit the digital word on the SDO pin to the DSP. The AD7723 also generates the frame synchronization signal that synchronizes the transfer of the 16-bit word from the AD7723 to the DSP. Depending on the serial mode used, SCO will have a frequency equal to CLKIN or equal to CLKIN/2. When SCO equals 19.2 MHz, the AD7723 can be interfaced to Analog Devices' ADSP-2106x SHARC DSP. With a 19.2 MHz master clock and SCO equal to CLKIN/2, the AD7723 can be interfaced with the ADSP-21xx family of DSPs, the DSP56002 and the TMS320C5x-57. When the AD7723 is used in the HALF_PWR mode, i.e., CLKIN is less than 10 MHz, then the AD7723 can be used with DSPs such as the TMS320C20/C25 and the DSP56000/1.
AD7723-to-ADSP-21xx Interface
(the receive data will be latched into the DSP on the falling clock edge), LAFS = 0 (the DSP begins reading the 16-bit word after the DSP has identified the frame sync signal rather than the DSP reading the word at the same instant as the frame sync signal has been identified), LRFS = 0 (RFS is active high). The AD7723 can be used in Modes 1, 2 or 3 when interfaced to the ADSP-2106x SHARC DSP.
AD7723-to-DSP56002 Interface
Figure 42 shows the AD7723-to-DSP56002 interface. To interface the AD7723 to the DSP56002, the ADC is operated in Mode 2 when the ADC is operated with a 19.2 MHz clock. The DSP56002 is configured as follows: SYN = 1 (synchronous mode), SCD1 = 0 (RFS is an input), GCK = 0 (a continuous serial clock is used), SCKD = 0 (the serial clock is external), WL1 = l, WL0 = 0 (transfers will be 16 bits wide), FSL1 = 0, FSL0 = 1 (the frame sync will be active at the beginning of each transfer). Alternatively, the DSP56002 can be operated in asynchronous mode (SYN = 0). In this mode, the serial clock for the receive section is input to the SCO pin. This is accomplished by setting bit SCDO to 0 (external Rx clock).
DSP56002 SDR SC1 SCK
Figure 41 shows the interface between the ADSP-21xx and the AD7723. The AD7723 is operated in Mode 2 so that SCO = CLKIN/2. For the ADSP-21xx, the bits in the serial port control register should be set up as RFSR = 1 (a frame sync is needed for each transfer), SLEN = 15 (16-bit word lengths), RFSW = 0 (normal framing mode for receive operations), INVRFS = 0 (active high RFS), IRFS = 0 (external RFS) and ISCLK = 0 (external serial clock).
ADSP-21xx DR RFS SCLK
AD7723
SDO FSO SCO
AD7723
SDO FSO SCO
Figure 42. AD7723-to-DSP56002 Interface
AD7723-to-TMS320C5x Interface
Figure 41. AD7723-to-ADSP-21xx Interface
AD7723-to-SHARC Interface
Figure 43 shows the AD7723-to-TMS320C5x interface. For the TMS320C5x, FSR and CLKR are automatically configured as inputs. The serial port is configured as follows: FO = 0 (16-bit word transfers), FSM = 1 (a frame sync occurs for each transfer).
TMS320C5x DR FSR CLKR
The interface between the AD7723 and the ADSP-2106x SHARC DSP is the same as shown in Figure 41 but, the DSP is configured as follows: SLEN = 15 (16-bit word transfers), SENDN = 0 (the MSB of the 16-bit word will be received by the DSP first), ICLK = 0 (an external serial clock will be used), RFSR = 0 (a frame sync is required for every word transfer), IRFS = 0 (the receive frame sync signal is external), CKRE = 0 REV. 0 -21-
AD7723
SDO FSO SCO
Figure 43. AD7723-to-TMS320C5x Interface
AD7723
GROUNDING AND LAYOUT
The analog and digital power supplies to the AD7723 are independent and separately pinned out to minimize coupling between analog and digital sections within the device. All the AD7723 AGND and DGND pins should be soldered directly to a ground plane to minimize series inductance. In addition, the ac path from any supply pin or reference pin (REF1 and REF2) through its decoupling capacitors to its associated ground must be made as short as possible (Figure 44). To achieve the best decoupling, place surface mount capacitors as close as possible to the device, ideally right up against the device pins. All ground planes must not overlap to avoid capacitive coupling. The AD7723's digital and analog ground planes must be connected at one place by a low inductance path, preferably right under the device. Typically, this connection will either be a trace on the Printed Circuit Board of 0.5 cm wide when the ground planes are on the same layer, or 0.5 cm wide minimum plated through holes when the ground planes are on different layers. Any external logic connected to the AD7723 should use a ground plane separate from the AD7723's digital ground plane. These two digital ground planes should also be connected at just one place. Separate power supplies for AVDD and DVDD are also highly desirable. The digital supply pin DVDD should be powered from a separate analog supply, but if necessary DVDD may share its power connection to AVDD. Refer to the connection diagram (Figure 44). The ferrites are also recommended to filter high frequency signals from corrupting the analog power supply. A minimum etch technique is generally best for ground planes as it gives the best shielding. Noise can be minimized by paying attention to the system layout and preventing different signals from interfering with each other. High level analog signals should be separated from low level analog signals, and both should be kept away from digital signals. In waveform sampling and reconstruction systems the sampling clock (CLKIN) is as vulnerable to noise as any analog signal. CLKIN should be isolated from the analog and digital systems. Fast switching signals like clocks should be shielded with their associated ground to avoid radiating noise to other sections of the board, and clock signals should never be routed near the analog inputs.
Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7723 to shield it from noise coupling. The power supply lines to the AD7723 should use as large a trace as possible (preferably a plane) to provide a low impedance path and reduce the effects of glitches on the power supply line. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board.
REF2 220nF 1F REF1 AVDD1 AGND1 +5V AGND1 AVDD 10 F 100nF 100nF 10nF AGND AVDD 10nF AD7723 ANALOG GROUND PLANE AD7723 DIGITAL GROUND PLANE 10 F 100nF 10nF AGND 10nF AGND2
10nF
10nF
DVDD DGND DGND
Figure 44. Reference and Power Supply Decoupling
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AD7723
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead Plastic Quad Flatpack (S-44)
C3230-8-4/98 PRINTED IN U.S.A.
0.548 (13.925) 0.546 (13.875) 0.398 (10.11) 0.390 (9.91)
33 34 23 22
0.096 (2.44) MAX 0.037 (0.94) 0.025 (0.64) SEATING PLANE 8 0.8
TOP VIEW
(PINS DOWN)
44
12 1 11
0.040 (1.02) 0.032 (0.81)
0.040 (1.02) 0.032 (0.81)
0.083 (2.11) 0.077 (1.96)
0.033 (0.84) 0.029 (0.74)
0.016 (0.41) 0.012 (0.30)
REV. 0
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